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general description the max1126 quad, 12-bit analog-to-digital converter(adc) features fully differential inputs, a pipelined architecture, and digital error correction. this adc is optimized for low-power, high-dynamic performance for medical imaging, communications, and instrumentation applications. the max1126 operates from a 1.7v to 1.9v single supply and consumes only 563mw while delivering a 69.9db signal-to-noise ratio (snr) at a 5.3mhz input frequency. in addition to low operating power, the max1126 features an 813? power-down mode for idle periods. an internal 1.24v precision bandgap reference sets the adc? full-scale range. a flexible reference structure allows the use of an external reference for applications requiring increased accuracy or a different input volt- age range. a single-ended clock controls the conversion process. an internal duty-cycle equalizer allows for wide varia- tions in input-clock duty cycle. an on-chip phase- locked loop (pll) generates the high-speed serial low-voltage differential signaling (lvds) clock. the max1126 provides serial lvds outputs for data, clock, and frame alignment signals. the output data is presented in two? complement or binary format. refer to the max1127 data sheet for a pin-compatible 65msps version of the max1126. the max1126 is available in a small, 10mm x 10mm x 0.9mm, 68-pin qfn package with exposed paddle and is specified for the extended industrial (-40? to +85?) temperature range. applications ultrasound and medical imagingpositron emission tomography (pet) imaging multichannel communication systems instrumentation features ? four adc channels with serial lvds/slvsoutputs ? excellent dynamic performance 69.9db snr at f in = 5.3mhz 93.7dbc sfdr at f in = 5.3mhz -90db channel isolation ? ultra-low power 135mw per channel (normal operation)1.5mw total (shutdown mode) ? accepts 20% to 80% clock duty cycle ? self-aligning data-clock to data-output interface ? fully differential analog inputs ? wide 1.4v p-p differential input voltage range ? internal/external reference option ? test mode for digital signal integrity ? lvds outputs support up to 30in fr-4 backplaneconnections ? small, 68-pin qfn with exposed paddle ? evaluation kit available (max1127evkit) max1126 quad, 12-bit, 40msps, 1.8v adc with serial lvds outputs ________________________________________________________________ maxim integrated products 1 ordering information 19-3143; rev 2; 9/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package max1126egk -40? to +85? 68 qfn 10mm xx 10mm x 0.9mm 35 out3n 36 out3p 37 ov dd 38 out2n 39 out2p 40 ov dd 41 framen 42 framep 43 ov dd 44 clkoutn 45 clkoutp 46 ov dd 47 out1n 48 out1p 49 ov dd 50 out0n 51 out0p 52 ov dd 53 pd0 54 pd1 55 pd2 56 pd3 57 pdall 58 av dd 59 av dd 60 av dd 61 av dd 62 av dd 63 64 lvdstest 65 gnd 66 refio 67 68 gnd 1gnd 2in0p 3in0n 4gnd 5in1p 6in1n 7gnd 8 av dd 9 av dd 10 av dd 11gnd 12in2p 13in2n 14gnd 15in3p 16in3n 17gnd 18 av dd 19 cmout 20 av dd 21 cv dd 22 gnd 23 clk 24 gnd 25 av dd 26 av dd 27 av dd 28 dt 29 30 pll0 31 pll1 32 pll2 33 pll3 34 ov dd slvs/lvds refadj t/b max1126 qfn 10mm x 10mm x 0.9mm ep pin configuration downloaded from: http:///
max1126 quad, 12-bit, 40msps, 1.8v adc with serial lvds outputs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics(av dd = 1.8v, ov dd = 1.8v, cv dd = 1.8v, gnd = 0, external v refio = 1.24v, refadj = av dd , c refio to gnd = 0.1?, f clk = 40mhz (50% duty cycle), dt = 0, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd to gnd.........................................................-0.3v to +2.0v cv dd to gnd ........................................................-0.3v to +3.6v ov dd to gnd ........................................................-0.3v to +2.0v in_p, in_n to gnd...................................-0.3v to (av dd + 0.3v) clk to gnd .............................................-0.3v to (cv dd + 0.3v) out_p, out_n, frame_, clkout_ to gnd................................-0.3v to (ov dd + 0.3v) dt, slvs/ lvds to gnd ...........................-0.3v to (av dd + 0.3v) pll0, pll1, pll2, pll3 to gnd .............-0.3v to (av dd + 0.3v) pd0, pd1, pd2, pd3, pdall to gnd......-0.3v to (av dd + 0.3v) t /b, lvdstest to gnd ...........................-0.3v to (av dd + 0.3v) refio, refadj, cmout, to gnd ..........-0.3v to (av dd + 0.3v) i.c. to gnd...............................................-0.3v to (av dd + 0.3v) continuous power dissipation (t a = +70?) 68-pin qfn 10mm x 10mm x 0.9mm (derated 41.7mw/? above +70?)........................3333.3mw operating temperature range ...........................-40? to +85? maximum junction temperature .....................................+150? storage temperature range .............................-65? to +150? lead temperature range (soldering, 10s)......................+300? parameter symbol conditions min typ max units dc accuracy resolution n 12 bits integral nonlinearity inl (note 2) 0.4 lsb differential nonlinearity dnl (note 2) 0.25 lsb offset error fixed external reference (note 2) 1 % fs gain error fixed external reference (note 2) -1.5 +0.9 +2.5 % fs analog inputs (in_p, in_n) input differential range v id differential input 1.4 v p-p common-mode voltage range v cmo (note 3) 0.76 v differential input impedance r in switched capacitor load 2 k ? differential input capacitance c in 12.5 pf conversion rate maximum conversion rate f smax 40 mhz minimum conversion rate f smin 4 mhz data latency 6.5 cycles dynamic characteristics (differential inputs, 4096-point fft) f in = 5.3mhz at -0.5dbfs 69.9 signal-to-noise ratio (note 2) snr f in = 19.3mhz at -0.5dbfs, t a +25? 66.7 69.2 db f in = 5.3mhz at -0.5dbfs 69.8 signal-to-noise and distortion(first four harmonics) (note 2) sinad f in = 19.3mhz at -0.5dbfs, t a +25? 66.7 69.1 db f in = 5.3mhz at -0.5dbfs 11.4 effective number of bits (note 2) enob f in = 19.3mhz at -0.5dbfs 11.3 bits downloaded from: http:///
max1126 quad, 12-bit, 40msps, 1.8v adc with serial lvds outputs _______________________________________________________________________________________ 3 electrical characteristics (continued)(av dd = 1.8v, ov dd = 1.8v, cv dd = 1.8v, gnd = 0, external v refio = 1.24v, refadj = av dd , c refio to gnd = 0.1?, f clk = 40mhz (50% duty cycle), dt = 0, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units f in = 5.3mhz at -0.5dbfs 93.7 spurious-free dynamic range(note 2) sfdr f in = 19.3mhz at -0.5dbfs, t a +25? 77.3 89 dbc f in = 5.3mhz at -0.5dbfs -91.5 total h ar m oni c d i stor ti on ( n ote 2) thd f in = 19.3mhz at -0.5dbfs, t a +25? -88.7 -76.3 dbc inter m od ul ati on d i stor ti on imd f 1 = 12.40125mhz at -6.5dbfs, f 2 = 13.60125mhz at -6.5dbfs ( n ote 2) 87.0 dbc third-order intermodulation im3 f 1 = 12.40125mhz at -6.5dbfs, f 2 = 13.60125mhz at -6.5dbfs ( n ote 2) 89.3 dbc aperture jitter t aj (note 2) < 0.4 ps rms aperture delay t ad (note 2) 1 ns small-signal bandwidth ssbw input at -20dbfs (notes 2 and 4) 100 mhz full-power bandwidth lsbw input at -0.5dbfs (notes 2 and 4) 100 mhz output noise in_p = in_n 0.45 lsb rms overdrive recovery time t or r s = 25 ? , c s = 50pf 1 clock cycles common-mode output (cmout) cmout output voltage v cmout 0.76 v internal reference (refadj = gnd, bypass refio to gnd with 0.1?) refadj internal reference modeenable voltage (note 5) 0.1 v refadj low-leakage current 1.6 ma refio output voltage v refio 1.18 1.24 1.30 v reference temperaturecoefficient tc refio 100 ppm/? external reference (refadj = av dd ) refadj external referencemode enable voltage (note 5) av dd - 0.1v v refadj high-leakage current 125 ? refio input voltage range 1.24 v refio input voltage tolerance 5% refio input current i refio < 1 ? clock input (clk) input high voltage v clkh 0.8 x av dd v input low voltage v clkl 0.2 x av dd v clock duty cycle 50 % clock duty-cycle tolerance ?0 % downloaded from: http:///
max1126 quad, 12-bit, 40msps, 1.8v adc with serial lvds outputs 4 _______________________________________________________________________________________ electrical characteristics (continued)(av dd = 1.8v, ov dd = 1.8v, cv dd = 1.8v, gnd = 0, external v refio = 1.24v, refadj = av dd , c refio to gnd = 0.1?, f clk = 40mhz (50% duty cycle), dt = 0, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units input at gnd 5 input leakage di in input at av dd 80 ? input capacitance dc in 5p f digital inputs (pll_, lvdstest, dt, slvs/ lvds , pd_, pdall, t /b) input high threshold v ih 0.8 x av dd v input low threshold v il 0.2 x av dd v input at gnd 5 input leakage di in input at av dd 80 ? input capacitance dc in 5p f lvds outputs (out_p, out_n, slvs/ lvds = 0 differential output voltage v ohdiff r term = 100 ? 250 450 mv output common-mode voltage v ocm r term = 100 ? 1.125 1.375 v rise time (20% to 80%) t r r term = 100 ? , c load = 5pf 150 ps fall time (80% to 20%) t f r term = 100 ? , c load = 5pf 150 ps slvs outputs (out_p, out_n, clkoutp, clkoutn, framep, framen), slvs/ lvds = 1, dt = 1 differential output voltage v ohdiff r term = 100 ? 205 mv output common-mode voltage v ocm r term = 100 ? 220 mv rise time (20% to 80%) t r r term = 100 ? , c load = 5pf 120 ps fall time (80% to 20%) t f r term = 100 ? , c load = 5pf 120 ps power-down pd fall to output enable t enable 132 ? pd rise to output disable t disable 10 ns power requirements av dd supply voltage av dd 1.7 1.8 1.9 v ov dd supply voltage ov dd 1.7 1.8 1.9 v cv dd supply voltage cv dd 1.7 1.8 3.6 v downloaded from: http:///
max1126 quad, 12-bit, 40msps, 1.8v adc with serial lvds outputs _______________________________________________________________________________________ 5 electrical characteristics (continued)(av dd = 1.8v, ov dd = 1.8v, cv dd = 1.8v, gnd = 0, external v refio = 1.24v, refadj = av dd , c refio to gnd = 0.1?, f clk = 40mhz (50% duty cycle), dt = 0, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units pdall = 0, all channelsactive 246 285 pdall = 0, all channelsactive, dt = 1 246 pdall = 0, 1 channel active 76 pdall = 0, pd[3:0] = 1111 20 ma av dd supply current i avdd f in = 19.3mhz at -0.5dbfs pdall = 1, global powerdown, pd[3:0] =1111, no clock input 438 ? pdall = 0, all channelsactive 51 57 pdall = 0, all channelsactive, dt = 1 63 pdall = 0, 1 channel active 35 pdall = 0, pd[3:0] = 1111 30 ma ov dd supply current i ovdd f in = 19.3mhz at -0.5dbfs pdall = 1, global power-down, pd[3:0] =1111, no clock input 375 ? cv dd supply current i cvdd cv dd is used only to bias esd-protection diodes on clk input, figure 2 0m a power dissipation p diss f in = 19.3mhz at -0.5dbfs 535 616 mw timing characteristics (note 6) data valid to clkout rise/fall t od f clk = 40mhz, figure 5 (notes 6 and 7) (t sample / 24) - 0. 15 t sample / 24 (t sample / 24) + 0.15 ns clkout output width high t ch figure 5 t s amp le / 12 ns clkout output width low t cl figure 5 t s amp le / 12 ns frame rise to clkout rise t cf figure 4 (note 7) (t sample / 24) - 0. 15 t sample / 24 ( t sample / 24) + 0.15 ns sample clk rise to frame rise t sf figure 4 (notes 7 and 8) (t sample / 2) +0.9 (t sample / 2) +1.3 (t sample / 2) +1.7 ns downloaded from: http:///
max1126 quad, 12-bit, 40msps, 1.8v adc with serial lvds outputs 6 _______________________________________________________________________________________ note 1: specifications at t a +25? are guaranteed by production testing. specifications at t a < +25? are guaranteed by design and characterization and not subject to production testing. note 2: see definition in the parameter definitions section. note 3: the max1126 internally sets the common-mode voltage to 0.76v (typ) (see figure 1). the common-mode voltage can beoverdriven to between 0.55v and 0.85v. note 4: limited by max1127evkit input circuitry. note 5: connect refadj to gnd directly to enable internal reference mode. connect refadj to av dd directly to disable the inter- nal bandgap reference and enable external reference mode. note 6: data valid to clkout rise/fall timing is measured from 50% of data output level to 50% of clock output level. note 7: guaranteed by design and characterization. not subject to production testing. note 8: sample clk rise to frame rise timing is measured from 50% of sample clock input level to 50% of frame output level. electrical characteristics (continued)(av dd = 1.8v, ov dd = 1.8v, cv dd = 1.8v, gnd = 0, external v refio = 1.24v, refadj = av dd , c refio to gnd = 0.1?, f clk = 40mhz (50% duty cycle), dt = 0, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units channel-to-channel matching crosstalk (note 2) -90 db gain matching f in = 19.3mhz (note 2) ?.1 db phase matching f in = 19.3.mhz (note 2) ? degrees downloaded from: http:///
max1126 quad, 12-bit, 40msps, 1.8v adc with serial lvds outputs _______________________________________________________________________________________ 7 fft plot (32,768-point data record) max1126 toc01 frequency (mhz) amplitude (dbfs) 20 481 2 16 -110 -90 -100 -80 -70 -50 -30 -10-60 -40 -20 0 -120 0 f clk = 40.96mhz f in = 5.30125mhz a in = -0.5dbfs snr = 69.88dbsinad = 69.85db thd = -91.46dbc sfdr = 93.65dbc hd2 hd3 fft plot (32,768-point data record) max1126 toc02 frequency (mhz) amplitude (dbfs) 20 481 2 16 -110 -90 -100 -80 -70 -50 -30 -10-60 -40 -20 0 -120 0 f clk = 40.96mhz f in = 19.00125mhz a in = -0.5dbfs snr = 69.20dbsinad = 69.16db thd = -88.74dbc sfdr = 89.04dbc hd2 hd3 crosstalk (4096-point data record) max1126 toc03 frequency (mhz) amplitude (dbfs) 481 2 16 -90 -100 -80 -70 -50 -30 -10-60 -40 -20 0 -110 02 0 measured on channel 2, with interfering signal on channel 0 f clk = 39.9997651mhz f in(in2) = 5.2831721mhz f in(in0) = 19.3260584mhz crosstalk (4096-point data record) max1126 toc04 frequency (mhz) amplitude (dbfs) 481 2 16 -90 -100 -80 -70 -50 -30 -10-60 -40 -20 0 -110 02 0 measured on channel 2, with interfering signal on channel 1 f clk = 39.9997651mhz f in(in2) = 5.2831721mhz f in(in1) = 19.3260584mhz crosstalk (4096-point data record) max1126 toc05 frequency (mhz) amplitude (dbfs) 481 2 16 -90 -100 -80 -70 -50 -30 -10-60 -40 -20 0 -110 02 0 measured on channel 2, with interfering signal on channel 3 f clk = 39.9997651mhz f in(in2) = 5.2831721mhz f in(in3) = 19.3260584mhz two-tone intermodulation distortion (32,768-point data record) max1126 toc06 frequency (mhz) amplitude (dbfs) 481 2 16 -110 -90 -100 -80 -70 -50 -30 -10-60 -40 -20 0 -120 02 0 f in(in1) = 12.40125mhz f in(in2) = 13.60125mhz a in1 = -6.5dbfs a in2 = -6.5dbfs imd = 87.0dbcim3 = 89.3dbc 1 100 1000 gain bandwidth plot max1126 toc07 analog input frequency (mhz) gain (db) 10 -7 -5-6 -4 -2-3 0 -1 1 -9 -8 full-powerbandwidth -0.5dbfs small-signalbandwidth -20dbfs t ypical operating characteristics (av dd = 1.8v, ov dd = 1.8v, cv dd = 1.8v, gnd = 0, external v refio = 1.24v, refadj = av dd , differential input at -0.5dbfs, f clk = 40mhz (50% duty cycle), dt = low, c load = 10pf, t a = +25?, unless otherwise noted.) downloaded from: http:///
max1126 quad, 12-bit, 40msps, 1.8v adc with serial lvds outputs 8 _______________________________________________________________________________________ signal-to-noise ratio vs. analog input frequency max1126 toc08 f in (mhz) snr (db) 150 125 75 100 50 25 63 64 65 66 67 68 69 70 71 7262 0 175 signal-to-noise plus distortion vs. analog input frequency max1126 toc09 f in (mhz) sinad (db) 150 125 75 100 50 25 63 64 65 66 67 68 69 70 71 7262 0 175 total harmonic distortion vs. analog input frequency max1126 toc10 f in (mhz) thd (dbc) 150 125 75 100 50 25 -95 -90 -85 -80 -75 -70 -65 -60 -55 -100 0 175 spurious-free dynamic range vs. analog input frequency max1126 toc11 f in (mhz) sfdr (dbc) 150 125 75 100 50 25 65 70 75 80 85 90 95 100 105 60 0 175 t ypical operating characteristics (continued) (av dd = 1.8v, ov dd = 1.8v, cv dd = 1.8v, gnd = 0, external v refio = 1.24v, refadj = av dd , differential input at -0.5dbfs, f clk = 40mhz (50% duty cycle), dt = low, c load = 10pf, t a = +25?, unless otherwise noted.) downloaded from: http:///
max1126 quad, 12-bit, 40msps, 1.8v adc with serial lvds outputs _______________________________________________________________________________________ 9 signal-to-noise ratio vs. analog input power analog input power (dbfs) snr (db) -5 -10 -25 -20 -15 37 42 52 5747 62 67 7232 -30 0 max1126 toc12 f in = 5.301935mhz signal-to-noise plus distortion vs. analog input power analog input power (dbfs) sinad (db) -5 -10 -25 -20 -15 37 42 52 5747 62 max1126 toc13 67 7232 -30 0 f in = 5.301935mhz total harmonic distortion vs. analog input power analog input power (dbfs) thd (dbc) -5 -10 -25 -20 -15 -90-95 -85 -75 -70-80 -65 -60 -55 -100 -30 0 max1126 toc14 f in = 5.301935mhz spurious-free dynamic range vs. analog input power analog input power (dbfs) sfdr (dbc) -5 -10 -25 -20 -15 6560 70 80 8575 90 95 100 55 -30 0 max1126 toc15 f in = 5.301935mhz t ypical operating characteristics (continued) (av dd = 1.8v, ov dd = 1.8v, cv dd = 1.8v, gnd = 0, external v refio = 1.24v, refadj = av dd , differential input at -0.5dbfs, f clk = 40mhz (50% duty cycle), dt = low, c load = 10pf, t a = +25?, unless otherwise noted.) downloaded from: http:///
max1126 quad, 12-bit, 40msps, 1.8v adc with serial lvds outputs 10 ______________________________________________________________________________________ signal-to-noise ratio vs. sampling rate max1126 toc16 f clk (mhz) snr (db) 35 30 20 25 10 15 5 63 64 65 66 67 68 69 70 71 7262 04 0 f in = 5.301935mhz signal-to-noise plus distortion vs. sampling rate max1126 toc17 f clk (mhz) sinad (db) 35 30 20 25 10 15 5 63 64 65 66 67 68 69 70 71 7262 04 0 f in = 5.301935mhz total harmonic distortion vs. sampling rate max1126 toc18 f clk (mhz) thd (dbc) 35 30 25 20 15 10 5 -100 -95 -90 -85 -80 -75 -105 04 0 f in = 5.301935mhz spurious-free dynamic range vs. sampling rate max1126 toc19 f clk (mhz) sfdr (dbc) 35 30 25 20 15 10 5 80 85 90 95 100 105 75 04 0 f in = 5.301935mhz t ypical operating characteristics (continued) (av dd = 1.8v, ov dd = 1.8v, cv dd = 1.8v, gnd = 0, external v refio = 1.24v, refadj = av dd , differential input at -0.5dbfs, f clk = 40mhz (50% duty cycle), dt = low, c load = 10pf, t a = +25?, unless otherwise noted.) downloaded from: http:///
max1126 quad, 12-bit, 40msps, 1.8v adc with serial lvds outputs ______________________________________________________________________________________ 11 signal-to-noise ratio vs. clock duty cycle clock duty cycle (%) snr (db) 60 40 50 65 6763 69 7164 66 68 70 7262 30 70 max1126 toc20 f in = 5.301935mhz signal-to-noise plus distortion vs. clock duty cycle clock duty cycle (%) sinad (db) 60 40 50 65 6763 69 7164 66 68 70 7262 30 70 max1126 toc21 f in = 5.301935mhz total harmonic distortion vs. clock duty cycle clock duty cycle (%) thd (dbc) 40 60 50 max1126 toc22 -95 -90 -100 -85 -80 -75 -105 30 70 f in = 5.301935mhz spurious-free dynamic range vs. clock duty cycle clock duty cycle (%) sfdr (dbc) 40 60 50 80 8575 90 95 100 70 30 70 max1126 toc23 f in = 5.301935mhz t ypical operating characteristics (continued) (av dd = 1.8v, ov dd = 1.8v, cv dd = 1.8v, gnd = 0, external v refio = 1.24v, refadj = av dd , differential input at -0.5dbfs, f clk = 40mhz (50% duty cycle), dt = low, c load = 10pf, t a = +25?, unless otherwise noted.) downloaded from: http:///
analog supply current vs. sampling rate f clk (mhz) i avdd (ma) max1126 toc28 240 250230 260 270220 35 30 25 20 40 digital supply current vs. sampling rate f clk (mhz) i ovdd (ma) max1126 toc29 20 4010 6030 50 70 0 35 30 25 20 40 max1126 quad, 12-bit, 40msps, 1.8v adc with serial lvds outputs 12 ______________________________________________________________________________________ t ypical operating characteristics (continued) (av dd = 1.8v, ov dd = 1.8v, cv dd = 1.8v, gnd = 0, external v refio = 1.24v, refadj = av dd , differential input at -0.5dbfs, f clk = 40mhz (50% duty cycle), dt = low, c load = 10pf, t a = +25?, unless otherwise noted.) signal-to-noise ratio vs. temperature temperature ( c) snr (db) -15 10 60 35 66 6864 70 7262 -40 85 max1126 toc24 f clk = 40.404040404mhz f in = 19.29204151mhz 4096-point data record signal-to-noise plus distortion vs. temperature temperature ( c) sinad (db) -15 10 60 35 66 6864 70 7262 -40 85 max1126 toc25 f clk = 40.404040404mhz f in = 19.29204151mhz 4096-point data record total harmonic distortion vs. temperature temperature ( c) thd (dbc) -15 10 60 35 -95 -90 -100 -85 -80 -75 -105 -40 85 max1126 toc26 f clk = 40.404040404mhz f in = 19.29204151mhz 4096-point data record spurious-free dynamic range vs. temperature temperature ( c) sfdr (dbc) -15 10 60 35 85 9080 75 95 100 70 -40 85 max1126 toc27 f clk = 40.404040404mhz f in = 19.29204151mhz 4096-point data record downloaded from: http:///
max1126 quad, 12-bit, 40msps, 1.8v adc with serial lvds outputs ______________________________________________________________________________________ 13 offset error vs. temperature temperature ( c) offset error (%fs) -15 10 60 35 -40 85 max1126 toc30 -0.015 -0.010 -0.005 0 0.005 0.010 0.015 0.020 -0.020 gain error vs. temperature temperature ( c) gain error (%fs) -15 10 60 35 0.6 0.80.4 0.2 0.5 0.70.3 0.1 0.9 1.0 0 -40 85 max1126 toc31 integral nonlinearity vs. digital output code max1126 toc32 digital output code inl (lsb) 3584 3072 2560 2048 1536 1024 512 -0.4 -0.2 0 0.2 0.4 0.6 -0.6 0 4096 differential nonlinearity vs. digital output code max1126 toc33 digital output code dnl (lsb) 3584 3072 2560 2048 1536 1024 512 0 4096 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 t ypical operating characteristics (continued) (av dd = 1.8v, ov dd = 1.8v, cv dd = 1.8v, gnd = 0, external v refio = 1.24v, refadj = av dd , differential input at -0.5dbfs, f clk = 40mhz (50% duty cycle), dt = low, c load = 10pf, t a = +25?, unless otherwise noted.) internal reference voltage vs. supply voltage supply voltage (v) v refio (v) 2.0 1.9 1.8 1.236 1.237 1.238 1.2391.235 1.7 2.1 max1126 toc34 av dd = ov dd internal reference voltage vs. temperature temperature ( c) v refio (v) 60 35 10 -15 1.23 1.24 1.25 1.261.22 -40 85 max1126 toc35 av dd = ov dd internal reference voltage vs. reference load current i refio ( a) v refio (v) 300 200 -300 -200 -100 0 100 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.401.00 -400 400 max1126 toc36 negative currentflows into refio downloaded from: http:///
max1126 quad, 12-bit, 40msps, 1.8v adc with serial lvds outputs 14 ______________________________________________________________________________________ t ypical operating characteristics (continued) (av dd = 1.8v, ov dd = 1.8v, cv dd = 1.8v, gnd = 0, external v refio = 1.24v, refadj = av dd , differential input at -0.5dbfs, f clk = 40mhz (50% duty cycle), dt = low, c load = 10pf, t a = +25?, unless otherwise noted.) cmout voltage vs. supply voltage max1126 toc37 supply voltage (v) v cmout (v) 2.0 1.9 1.8 0.757 0.759 0.761 0.763 0.7650.755 1.7 2.1 av dd = ov dd cmout voltage vs. temperature max1126 toc38 temperature ( c) v cmout (v) 60 35 10 -15 0.757 0.759 0.761 0.763 0.7650.755 -40 85 av dd = ov dd cmout voltage vs. load current max1126 toc39 i cmout ( a) v cmout (v) 2500 2000 1500 1000 500 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 0 3000 negative currentflows into cmout pin name function 1, 4, 7, 11,14, 17, 22, 24, 65, 68 gnd ground. connect all gnd pins to the same potential. 2 in0p channel 0 positive analog input 3 in0n channel 0 negative analog input 5 in1p channel 1 positive analog input 6 in1n channel 1 negative analog input 8, 9, 10, 18, 20, 25, 26, 27, 58?2 av dd analog power input. connect av dd to a 1.7v to 1.9v power supply. bypass each av dd to gnd with a 0.1? capacitor as close to the device as possible. bypass the av dd power plane to the gnd ground plane with a bulk 2.2? capacitor as close to the device as possible. connect all av dd pins to the same potential. 12 in2p channel 2 positive analog input 13 in2n channel 2 negative analog input 15 in3p channel 3 positive analog input 16 in3n channel 3 negative analog input 19 cmout common-mode reference voltage output. bypass cmout to gnd with a 0.1? capacitor. 21 cv dd clock power input. connect cv dd to a 1.7v to 3.6v supply. bypass cv dd to gnd with a 0.1? capacitor in parallel with a 2.2? capacitor. install the bypass capacitors as close to the device as possible. 23 clk single-ended cmos clock input 28 dt double termination select input. drive dt high to select the internal 100 ? termination between the differential output pairs. drive dt low to select no internal output termination. pin description downloaded from: http:///
max1126 quad, 12-bit, 40msps, 1.8v adc with serial lvds outputs ______________________________________________________________________________________ 15 pin name function 29 slvs/ lvds differential output signal format select input. drive slvs/ lvds high to select slvs outputs. drive slvs/ lvds low to select lvds outputs. 30 pll0 pll control input 0. pll0 is reserved for factory testing only and must always be connected to gnd. 31 pll1 pll control input 1. see table 1 for details. 32 pll2 pll control input 2. see table 1 for details. 33 pll3 pll control input 3. see table 1 for details. 34, 37, 40,43, 46, 49, 52 ov dd output-driver power input. connect ov dd to a 1.7v to 1.9v power supply. bypass each ov dd to gnd with a 0.1? capacitor as close to the device as possible. bypass the ov dd power plane to the gnd ground plane with a bulk 2.2? capacitor as close to the device as possible. connect all ov dd pins to the same potential. 35 out3n channel 3 negative lvds/slvs output 36 out3p channel 3 positive lvds/slvs output 38 out2n channel 2 negative lvds/slvs output 39 out2p channel 2 positive lvds/slvs output 41 framen negative frame alignment lvds/slvs output. a rising edge on the differential frame output alignsto a valid d0 in the output data stream. 42 framep positive frame alignment lvds/slvs output. a rising edge on the differential frame output aligns toa valid d0 in the output data stream. 44 clkoutn negative lvds/slvs serial clock output 45 clkoutp positive lvds/slvs serial clock output 47 out1n channel 1 negative lvds/slvs output 48 out1p channel 1 positive lvds/slvs output 50 out0n channel 0 negative lvds/slvs output 51 out0p channel 0 positive lvds/slvs output 53 pd0 channel 0 power-down input. drive pd0 high to power-down channel 0. drive pd0 low for normaloperation. 54 pd1 channel 1 power-down input. drive pd1 high to power-down channel 1. drive pd1 low for normaloperation. 55 pd2 channel 2 power-down input. drive pd2 high to power-down channel 2. drive pd2 low for normaloperation. 56 pd3 channel 3 power-down input. drive pd3 high to power-down channel 3. drive pd3 low for normaloperation. 57 pdall global power-down input. drive pdall high to power-down all channels and reference. drive pdalllow for normal operation. 63 t /b output format select input. drive t /b high to select binary output format. drive t /b low to select two? complement output format. pin description (continued) downloaded from: http:///
max1126 quad, 12-bit, 40msps, 1.8v adc with serial lvds outputs 16 ______________________________________________________________________________________ lvds/slvs output drivers reference system pll 6x clock circuitry power control refio refadj in0p cmout in0n in1p in1n in2p in2n in3p in3n clk pdall pd0 pd1 pd2 pd3 out0pout0n out1p out1n out2p out2n out3p out3n clkoutp clkoutn ov dd av dd gnd cv dd pll3 pll0 pll1 pll2 t/b lvdstest framep framen dt output control max1126 t/h icmv* *icmv = input common-mode voltage (internally generated) 12-bit pipeline adc 12:1 serializer t/h 12-bit pipeline adc 12:1 serializer t/h 12-bit pipeline adc 12:1 serializer t/h 12-bit pipeline adc 12:1 serializer slvs/lvds functional diagram pin name function 64 lvdstest lvds test pattern enable input. drive lvdstest high to enable the output test pattern(000010111101 msb lsb). as with the analog conversion results, the test pattern data is output lsb first. drive lvdstest low for normal operation. 66 refio reference input/output. for internal reference operation (refadj = gnd), the reference output voltage is 1.24v. for external reference operation (refadj = av dd ), apply a stable reference voltage at refio. bypass to gnd with a 0.1? capacitor. 67 refadj internal/external reference mode select input. for internal reference mode, connect refadj directlyto gnd. for external reference mode, connect refadj directly to av dd . for reference-adjust mode, see the full-scale range adjustments using the internal reference section. ? p exposed paddle. ep is internally connected to gnd. externally connect ep to gnd to achievespecified performance. pin description (continued) downloaded from: http:///
max1126 quad, 12-bit, 40msps, 1.8v adc with serial lvds outputs ______________________________________________________________________________________ 17 detailed description the max1126 adc features fully differential inputs, apipelined architecture, and digital error correction for high-speed signal conversion. the adc pipeline archi- tecture moves the samples taken at the inputs through the pipeline stages every half clock cycle. the convert- ed digital results are serialized and sent through the lvds/slvs output drivers. the total latency from input to output is 6.5 input clock cycles. the max1126 offers four separate fully differential channels with synchronized inputs and outputs. configure the outputs for binary or two? complement with the t /b digital input. power-down each channel individually or globally to minimize power consumption. input circuit figure 1 displays a simplified functional diagram of theinput t/h circuits. in track mode, switches s1, s2a, s2b, s4a, s4b, s5a, and s5b are closed. the fully differential circuits sample the input signals onto the two capacitors (c2a and c2b) through switches s4a and s4b. s2a and s2b set the common mode for the operational transcon- ductance amplifier (ota), and open simultaneously withs1, sampling the input waveform. switches s4a, s4b, s5a, and s5b are then opened before switches s3a and s3b connect capacitors c1a and c1b to the output of the amplifier and switch s4c is closed. the resulting dif- ferential voltages are held on capacitors c2a and c2b. the amplifiers charge capacitors c1a and c1b to the same values originally held on c2a and c2b. these values are then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs.analog inputs in_p to in_n are driven differentially. for differential inputs, balance the input impedance of in_p and in_n for optimum performance. the max1126 analog inputs are self-biased at a com- mon-mode voltage of 0.76v (typ) and allow a differen- tial input voltage swing of 1.4v p-p . the common-mode voltage can be overdriven to between 0.55v and 0.85v.drive the analog inputs of the max1126 in ac-coupled configuration to achieve best dynamic performance. see the using transformer coupling section for a detailed discussion of this configuration. max1126 in_p in_n ota av dd gnd c2a s4b s4c s1 c2b s4a c1a s2a s5a s3a s3b s5b c1b s2b internal bias* out internally generated common-mode level* switches shown in track mode internally generated common-mode level* internal common-mode bias* internal common-mode bias* *not externally accessible internal bias* out figure 1. internal input circuitry downloaded from: http:///
max1126 quad, 12-bit, 40msps, 1.8v adc with serial lvds outputs 18 ______________________________________________________________________________________ reference configurations (refio and refadj) the max1126 provides an internal 1.24v bandgap ref-erence or can be driven with an external reference volt- age. the max1126 full-scale analog differential input range is ?sr. full-scale range (fsr) is given by the following equation: where v refio is the voltage at refio, generated inter- nally or externally. for a v refio = 1.24v, the full-scale input range is ?00mv (1.4v p-p ). internal reference mode connect refadj to gnd to use the internal bandgap reference directly. the internal bandgap reference gen- erates refio to be 1.24v with a 100ppm/? tempera- ture coefficient in internal reference mode. connect an external 0.1? bypass capacitor from refio to gnd for stability. refio sources up to 200? and sinks upto 200? for external circuits, and refio has a load regulation of 83mv/ma. the global power-down input (pdall) enables and disables the reference circuit. refio has > 1m ? resistance to gnd when the max1126 is in power-down mode. the internal refer- ence circuit requires 132? to power-up and settle when power is applied to the max1126 or when pdall transitions from high to low. to compensate for gain errors or to decrease or increase the adc? full-scale range (fsr), add an external resistor between refadj and gnd or refadj and refio. this adjusts the internal reference value of the max1126 by up to ?% of its nominal value. see the full-scale range adjustments using the internal reference section. external reference mode the external reference mode allows for more controlover the max1126 reference voltage and allows multi- ple converters to use a common reference. connect refadj to av dd to disable the internal reference and enter external reference mode. apply a stable 1.18v to1.30v source at refio. bypass refio to gnd with a 0.1? capacitor. the refio input impedance is > 1m ? . clock input (clk) the max1126 accepts a cmos-compatible clock sig-nal with a wide 20% to 80% input-clock duty cycle. drive clk with an external single-ended clock signal. figure 2 shows the simplified clock input diagram. low clock jitter is required for the specified snr perfor- mance of the max1126. analog input sampling occurs on the rising edge of clk, requiring this edge to pro- vide the lowest possible jitter. jitter limits the maximum snr performance of any adc according to the follow- ing relationship: where f in represents the analog input frequency and t j is the total system clock jitter. clock jitter is especiallycritical for undersampling applications. for example, assuming that clock jitter is the only noise source, to obtain the specified 69.2db of snr with an input fre- quency of 19.3mhz, the system must have less than 2.8ps rms of clock jitter. in actuality, there are other noise sources, such as thermal noise and quantizationnoise, that contribute to the system noise requiring the clock jitter to be less than 1.1ps rms to obtain the speci- fied 69.2db of snr at 19.3mhz. snr ft in j = ?? ? ?? ? 20 1 2 log fsr mv x v v refio = 700 124 . max1126 duty-cycle equalizer av dd cv dd clk gnd figure 2. clock input circuitry clock input range (mhz) pll1 pll2 pll3 min max 000 not used 001 32.5 40.0 010 22.5 32.5 011 16.3 22.5 100 11.3 16.3 101 8.1 11.3 110 5.6 8.1 111 4.0 5.6 table 1. pll1, pll2, and pll3 configuration * pll0 is reserved for factory testing and must always be con- nected to gnd. downloaded from: http:///
max1126 quad, 12-bit, 40msps, 1.8v adc with serial lvds outputs ______________________________________________________________________________________ 19 pll inputs (pllo?ll3) the max1126 features a pll that generates an outputclock signal with 6 times the frequency of the input clock. the output clock signal is used to clock data out of the max1126 (see the system timing requirements section). set the pll1, pll2, and pll3 bits accordingto the input clock range provided in table 1. pll0 is reserved for factory testing and must always be con- nected to gnd. system timing requirements figure 3 shows the relationship between the analoginputs, input clock, frame alignment output, serial clock output, and serial data output. the differential analog input (in_p and in_n) is sampled on the rising edge of the clk signal and the resulting data appears at the digital outputs 6.5 clock cycles later. figure 4 provides a detailed, two-conversion timing diagram of the rela- tionship between the inputs and the outputs. output data for sample n - 6 output data for sample n *duty cycle varies depending on input clock frequency. clk n n + 2 n + 1 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 6.5 clock-cycle data latency t sample (v in_p - v in_n ) (v framep - v framen )* (v clkoutp - v clkoutn ) (v out_p - v out_n ) figure 3. global timing diagram n n + 2 n + 1 *duty cycle depends on input clock frequency. t cf (v in_p - v in_n ) clk (v framep - v framen ) (v clkoutp - v clkoutn ) (v out_p - v out_n ) d5 n-7 d6 n-7 d7 n-7 d8 n-7 d9 n-7 d10 n-7 d11 n-7 d0 n-6 d1 n-6 d2 n-6 d3 n-6 d4 n-6 d5 n-6 d6 n-6 d7 n-6 d8 n-6 d9 n-6 d10 n-6 d11 n-6 d0 n-5 d1 n-5 d2 n-5 d3 n-5 d4 n-5 d5 n-5 d6 n-5 t sample t sf figure 4. detailed two-conversion timing diagram downloaded from: http:///
max1126 quad, 12-bit, 40msps, 1.8v adc with serial lvds outputs 20 ______________________________________________________________________________________ clock output (clkoutp, clkoutn) the max1126 provides a differential clock output thatconsists of clkoutp and clkoutn. as shown in figure 4, the serial output data is clocked out of the max1126 on both edges of the clock output. the fre- quency of the output clock is 6 times the frequency of clk. frame alignment output (framep, framen) the max1126 provides a differential frame alignmentsignal that consists of framep and framen. as shown in figure 4, the rising edge of the frame align- ment signal corresponds to the first bit (d0) of the 12-bit serial data stream. the frequency of the frame alignment signal is identical to the frequency of the sample clock. serial output data (out_p, out_n) the max1126 provides its conversion results throughindividual differential outputs consisting of out_p and out_n. the results are valid 6.5 input clock cycles after the sample is taken. as shown in figure 3, the out- put data is clocked out on both edges of the output clock, lsb (d0) first. figure 5 provides the detailed ser- ial output timing diagram. output data format ( t /b), transfer functions the max1126 output data format is either offset binaryor two? complement, depending on the logic input t /b. with t /b low, the output data format is two? comple- ment. with t /b high, the output data format is offset binary. the following equations, table 2, figure 6, andfigure 7 define the relationship between the digital output and the analog input. for two? complement ( t /b = 0): and for offset binary ( t /b = 1): where code 10 is the decimal equivalent of the digital output code as shown in table 2. fsr is the full-scalerange as shown in figures 6 and 7. keep the capacitive load on the max1126 digital out- puts as low as possible. lvds and slvs signals (slvs/ lvds ) drive slvs/ lvds low for lvds or drive slvs/ lvds high for scalable low-voltage signaling (slvs) levels atthe max1126 outputs (out_p, out_n, clkoutp, clkoutn, framep, and framen). for slvs levels, vv fsr code in p in n __ = 2 2048 4096 10 vv fsr code in p in n __ = 2 4096 10 (v clkoutp - v clkoutn ) (v out_p - v out_n ) t ch t cl t od t od d0 d1 d2 d3 figure 5. serialized output detailed timing diagram two? complement digital output code ( t /b = 0) offset binary digital output code ( t /b = 1) binary d11 d0 hexadecimal equivalent of d11 d0 decimal equivalent of d11 d0 binary d11 d0 hexadecimal equivalent of d11 d0 decimal equivalent of d11 d0 v in_p - v in_p (mv) (v refio = 1.24v) 0111 1111 1111 0x7ff +2047 1111 1111 1111 0xfff +4095 +699.66 0111 1111 1110 0x7fe +2046 1111 1111 1110 0xffe +4094 +699.32 0000 0000 0001 0x001 +1 1000 0000 0001 0x801 +2049 +0.34 0000 0000 0000 0x000 0 1000 0000 0000 0x800 +2048 0 1111 1111 1111 0xfff -1 0111 1111 1111 0x7ff +2047 -0.34 1000 0000 0001 0x801 -2047 0000 0000 0001 0x001 +1 -699.66 1000 0000 0000 0x800 -2048 0000 0000 0000 0x000 0 -700.00 table 2. output code table (v refio = 1.24v) downloaded from: http:///
max1126 quad, 12-bit, 40msps, 1.8v adc with serial lvds outputs ______________________________________________________________________________________ 21 enable double termination by driving dt high. see the electrical characteristics table for lvds and slvs out- put voltage levels. lvds test pattern (lvdstest) drive lvdstest high to enable the output test patternon all lvds or slvs output channels. the output test pattern is 0000 1011 1101 msb lsb. as with the ana- log conversion results, the test pattern data is output lsb first. drive lvdstest low for normal operation(test pattern disabled). common-mode output voltage (cmout) cmout provides a common-mode reference for dc- coupled analog inputs. if the input is dc-coupled, match the output common-mode voltage of the circuit driving the max1126 to the output voltage at v cmout to within ?0mv. it is recommended that the outputcommon-mode voltage of the driving circuit be derived from cmout. double termination (dt) as shown in figure 8, the max1126 offers an optional,internal 100 ? termination between the differential output pairs (out_p and out_n, clkoutp and clkoutn, framep and framen). in addition to the termination at the end of the line, a second termination directly at the outputs helps eliminate unwanted reflec- tions down the line. this feature is useful in applications where trace lengths are long (> 5in) or with mis- matched impedance. drive dt high to select double termination, or drive dt low to disconnect the internal termination resistor (single termination). selecting dou- ble termination increases the ov dd supply current (see the electrical characteristics table). power-down modes the max1126 offers two types of power-down inputs,pd0?d3 and pdall. the power-down modes allow the max1126 to efficiently use power by transitioning to a low-power state when conversions are not required. differential input voltage (lsb) -2045 +2047 +2045 -1 0 +1 -2047 0x800 0x801 0x802 0x803 0x7ff0x7fe 0x7fd 0xfff 0x000 0x001 fsr fsr 1 lsb = 2 x fsr 4096 fsr = 700mv x v refio 1.24v two's complement output code (lsb) figure 6. bipolar transfer function with two? complementoutput code ( t /b = 0) differential input voltage (lsb) -2045 +2047 +2045 -1 0 +1 -2047 0x000 0x800 0x002 0x003 0xfff0xffe 0xffd 0x7ff 0x800 0x801 fsr fsr 1 lsb = 2 x fsr 4096 fsr = 700mv x v refio 1.24v offset binary output code (lsb) figure 7. bipolar transfer function with offset binary outputcode ( t /b = 1) max1126 100 ? 100 ? out_p/clkoutp/ framep out_n/ clkoutn/ framen dt switches are closed when dt is high. switches are open when dt is low. z 0 = 50 ? z 0 = 50 ? figure 8. double termination downloaded from: http:///
max1126 quad, 12-bit, 40msps, 1.8v adc with serial lvds outputs 22 ______________________________________________________________________________________ independent channel power-down (pd0?d3) pd0?d3 control the power-down mode of each chan- nel independently. drive a power-down input high to power down its corresponding input channel. for exam- ple, to power down channel 1, drive pd1 high. drive a power-down input low to place the corresponding input channel in normal operation. the differential output impedance of a powered-down output channel is approximately 378 ? , when dt is low. the output imped- ance of out_p, with respect to out_n, is 100 ? when dt is high. see the electrical characteristics table for typical supply currents with powered-down channels.the state of the internal reference is independent of the pd0?d3 inputs. to power down the internal reference circuitry, drive pdall high (see the global power- down (pdall) section). global power-down (pdall) pdall controls the power-down mode of all channelsand the internal reference circuitry. drive pdall high to enable global power-down. in global power-down mode, the output impedance of all the lvds/slvs outputs is approximately 378 ? , if dt is low. the output impedance of the differential lvds/slvs outputs is 100 ? when dt is high. see the electrical characteristics table for typical supply currents with global power-down. the following list shows the state of the analog inputs and digital out- puts in global power-down mode: in_p, in_n analog inputs are disconnected from theinternal input amplifier. refio has > 1m ? resistance to gnd. out_p, out_n, clkoutp, clkoutn, framep,and framen have approximately 378 ? between the output pairs when dt is low. when dt is high, the dif- ferential output pairs have 100 ? between each pair. when operating from the internal reference, the wake- up time from global power-down is typically 132?. when using an external reference, the wake-up time is dependent on the external reference drivers. applications information full-scale range adjustments using the internal reference the max1126 supports a full-scale adjustment range of 10% (5%). to decrease the full-scale range, add a 25k ? to 250k ? external resistor or potentiometer (r adj ) between refadj and gnd. to increase the full-scale range, add a 25k ? to 250k ? resistor between refadj and refio. figure 9 shows the two possible configurations. the following equations provide the relationship between r adj and the change in the analog full-scale range: for r adj connected between refadj and refio, and for r adj connected between refadj and gnd. fsr v k r adj = ?? ? ?? ? 07 1 125 . . ? fsr v k r adj =+ ?? ? ?? ? 07 1 125 . . ? reference buffer refio refadj av cc av cc / 2 control line to disable reference buffer adc full-scale = reft - refb g 1v 0.1 f reference- scaling amplifier reft refb 25k ? to 250k ? 25k ? to 250k ? max1126 figure 9. circuit suggestions to adjust the adc? full-scalerange downloaded from: http:///
max1126 quad, 12-bit, 40msps, 1.8v adc with serial lvds outputs ______________________________________________________________________________________ 23 using transformer coupling an rf transformer (figure 10) provides an excellentsolution to convert a single-ended input source signal to a fully differential signal, required by the max1126 for optimum performance. the max1126 input com- mon-mode voltage is internally biased to 0.76v (typ) with f clk = 40mhz. although a 1:1 transformer is shown, a step-up transformer can be selected toreduce the drive requirements. a reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. grounding, bypassing, and board layout the max1126 requires high-speed board layout designtechniques. refer to the max1127 ev kit data sheet for a board layout reference. locate all bypass capacitors as close to the device as possible, preferably on the same side as the adc, using surface-mount devices for minimum inductance. bypass av dd to gnd with a 0.1? ceramic capacitor in parallel with a 2.2? ceramic capacitor. bypass ov dd to gnd with a 0.1? ceramic capacitor in parallel with a 2.2? ceramic capacitor. bypass cv dd to gnd with a 0.1? ceramic capacitor in parallel with a 2.2? ceramic capacitor. multilayer boards with ample ground and power planesproduce the highest level of signal integrity. connect max1126 ground pins and the exposed backside pad- dle to the same ground plane. the max1126 relies on the exposed backside paddle connection for a low- inductance ground connection. isolate the groundplane from any noisy digital system ground planes. route high-speed digital signal traces away from the sensitive analog traces. keep all signal lines short and free of 90 turns. ensure that the differential analog input network layout is symmetric and that all parasitics are balanced equal- ly. refer to the max1126 ev kit data sheet for an exam- ple of symmetric input layout. parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on anactual transfer function from a straight line. for the max1126, this straight line is between the end points of the transfer function, once offset and gain errors have been nullified. inl deviations are measured at every step and the worst-case deviation is reported in the electrical characteristics table. differential nonlinearity (dnl) differential nonlinearity is the difference between anactual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. for the max1126, dnl deviations are measured at every step and the worst-case deviation is reported in the electrical characteristics table. offset error offset error is a figure of merit that indicates how wellthe actual transfer function matches the ideal transfer function at a single point. for the max1126, the ideal midscale digital output transition occurs when there is -1/2 lsb across the analog inputs (figures 6 and 7). bipolar offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point. gain error gain error is a figure of merit that indicates how well theslope of the actual transfer function matches the slope of the ideal transfer function. for the max1126, the gain error is the difference of the measured full-scale and zero-scale transition points minus the difference of the ideal full-scale and zero-scale transition points. max1126 v in 0.1 f 0.1 f n.c. 12 3 65 4 t1 minicircuits adt1-1wt 10 ? 10 ? 39pf39pf in_pin_n figure 10. transformer-coupled input drive downloaded from: http:///
max1126 quad, 12-bit, 40msps, 1.8v adc with serial lvds outputs 24 ______________________________________________________________________________________ for the bipolar devices (max1126), the full-scale transi-tion point is from 0x7fe to 0x7ff for two? complement output format (0xffe to 0xfff for offset binary) and the zero-scale transition point is from 0x800 to 0x801 for two? complement (0x000 to 0x001 for offset binary). crosstalk crosstalk indicates how well each analog input is isolat-ed from the others. for the max1126, a 5.3mhz, -0.5dbfs analog signal is applied to one channel while a 19.3mhz, -0.5dbfs analog signal is applied to all other channels. an fft is taken on the channel with the 5.3mhz analog signal. from this fft, the crosstalk is measured as the difference in the 5.3mhz and 19.3mhz amplitudes. aperture delay aperture delay (t ad ) is the time defined between the rising edge of the sampling clock and the instant whenan actual sample is taken. see figure 10. aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in the aperture delay. see figure 11. signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digitalsamples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adc? reso- lution (n bits): snr db[max] = 6.02 db x n + 1.76 db in reality, there are other noise sources besides quantiza- tion noise: thermal noise, reference noise, clock jitter, etc. for the max1126, snr is computed by taking the ratio of the rms signal to the rms noise. rms noise includes all spectral components to the nyquist fre- quency excluding the fundamental, the first six harmon- ics (hd2?d7), and the dc offset. signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms sig-nal to the rms noise plus distortion. rms noise plus distortion includes all spectral components to the nyquist frequency, excluding the fundamental and the dc offset. effective number of bits (enob) enob specifies the dynamic performance of an adc ata specific input frequency and sampling rate. an ideal adc? error consists of quantization noise only. enob for a full-scale sinusoidal input waveform is computed from: total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmon- ics of the input signal to the fundamental itself. this is expressed as: thd vvvvvv v = +++++ ?? ?? ?? ?? 20 2 2 3 2 4 2 5 2 6 2 7 2 1 log enob sinad = ?? ? ?? ? 176 602 . . clk analog input sampled d ata t/h t ad hold track hold t aj figure 11. aperture jitter/delay specifications downloaded from: http:///
spurious-free dynamic range (sfdr) sfdr is the ratio expressed in decibels of the rmsamplitude of the fundamental (maximum signal compo- nent) to the rms value of the next-largest spurious component, excluding dc offset. sfdr is specified in decibels relative to the carrier (dbc). intermodulation distortion (imd) imd is the total power of the im2 to im5 intermodulationproducts to the nyquist frequency relative to the total input power of the two input tones, f1 and f2. the indi- vidual input tone levels are at -6.5dbfs. the intermodu- lation products are as follows: 2nd-order intermodulation products (im2): f1 + f2, f2 - f1 3rd-order intermodulation products (im3): 2 x f1 - f2,2 x f2 - f1, 2 x f1 + f2, 2 x f2 + f1 4th-order intermodulation products (im4): 3 x f1 - f2,3 x f2 - f1, 3 x f1 + f2, 3 x f2 + f1 5th-order intermodulation products (im5): 3 x f1 - 2 xf2, 3 x f2 - 2 x f1, 3 x f1 + 2 x f2, 3 x f2 + 2 x f1 third-order intermodulation (im3) im3 is the total power of the 3rd-order intermodulationproduct to the nyquist frequency relative to the total input power of the two input tones f1 and f2. the indi- vidual input tone levels are at -6.5dbfs. the 3rd-order intermodulation products are 2 x f1 - f2, 2 x f2 - f1, 2 x f1 + f2, 2 x f2 + f1. small-signal bandwidth a small -20dbfs analog input signal is applied to anadc so the signal? slew rate does not limit the adc? performance. the input frequency is then swept up to the point where the amplitude of the digitized conver- sion result has decreased by 3db. full-power bandwidth a large -0.5dbfs analog input signal is applied to anadc, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3db. this point is defined as full- power input bandwidth frequency. gain matching gain matching is a figure of merit that indicates howwell the gain of all four adc channels is matched to each other. for the max1126, gain matching is mea- sured by applying the same 19.3mhz, -0.5dbfs analog signal to all analog input channels. these analog inputs are sampled at 40mhz and the maximum deviation in amplitude is reported in db as gain matching in the electrical characteristics table. phase matching phase matching is a figure of merit that indicates howwell the phase of all four adc channels is matched to each other. for the max1126, phase matching is mea- sured by applying the same 19.3mhz, -0.5dbfs analog signal to all analog input channels. these analog inputs are sampled at 40mhz and the maximum deviation in phase is reported in degrees as phase matching in the electrical characteristics table. max1126 quad, 12-bit, 40msps, 1.8v adc with serial lvds outputs ______________________________________________________________________________________ 25 downloaded from: http:///
max1126 quad, 12-bit, 40msps, 1.8v adc with serial lvds outputs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 26 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .) 68l qfn.eps c 1 2 21-0122 package outline, 68l qfn, 10x10x0.9 mm c 1 2 21-0122 package outline, 68l qfn, 10x10x0.9 mm note: for the max1126 exposed pad variation, the package code is g6800-4. downloaded from: http:///

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